Home Delay Aware Topology Generation for Network on Chip Book ISBN-10 3659693022, ISBN-13 978-3659693

Delay Aware Topology Generation for Network on Chip

Description

Paperback: 72 pages
Publisher: LAP LAMBERT Academic Publishing (September 3, 2015)
Language: English
ISBN-10: 3659693022
ISBN-13: 978-3659693021
Product Dimensions: 5.9 x 0.2 x 8.7 inches
Format: PDF ePub TXT book

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Book Description
Additional Information

Network-on-Chip (NoC) is a scalable bandwidth requirement that using on-chip packet-switched micro-network of interconnects. NoC are based on System-on-Chips(SoCs) that traditionally large-scale multi-processors and distributed computing networks. The NoC performances analysis were evaluated in terms of throughput, queue size, loss and wait time. Meanwhile, Video Object Plane Decoder (VOPD) with 16 cores were used to measured the delay aware topo...

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